1. Field of the Invention
The present invention is directed generally to electrostatic discharge (ESD) protection circuits for input/output (I/O) devices, and more particularly, to improving ESD robustness in I/O cell libraries using novel layout techniques to implement a turn-on retraining arrangement that reduces the turn-on speed or increases the breakdown voltage of a MOS transistor.
2. Description of the Related Art
The ESD robustness of CMOS integrated circuits (IC) has been found to be seriously degraded due to deep-submicron CMOS technologies. To improve the ESD robustness of the output transistors, the ESD-implant process and the silicide-blocking process have been widely implemented in the deep-submicron CMOS technologies. In addition to the process modification to improve the ESD robustness of the output buffers, the symmetrical layout structure had been emphasized to realize the large-dimension output transistors by ensuring the uniform turn-on phenomenon along the multiple fingers of the output transistor. To further enhance the uniform turn-on phenomenon among the multiple fingers of the output transistors, a gate-coupling design had been reported to achieve uniform ESD power distribution on large-dimension output transistors.
General circuit diagrams of the output cell, input cell, and I/O bidirectional cell in a cell library are shown in FIGS. 1(a)-(c), respectively. In a general application, the output buffers in a cell library have different driving specifications. For instance, the output buffers in a typical library may have the different driving capabilities of e.g., 2 mA, 4 mA, 8 mA, or 24 mA. To meet these different types of current specification, different numbers of fingers in the MOS device of the cell are provided to drive current to, or sink current from, the pad. An example of the finger numbers of the different I/O cells in a 0.35-μm cell library used to provide the driving/sinking current are shown in TABLE 1.
TABLE 1CurrentFinger NumberSpecificationxpxnypyninput cell0014144 mA2112138 mA42101210 mA5391114 mA7471018 mA955924 mA12628
Wherein W/L=35 μm/0.5 μm for each finger, and the xp (xn) is the number of fingers in the output PMOS (NMOS) layout, which are used to generate the output current to the pad.
However, the cell layouts of the output buffers with different driving capabilities are all drawn in the same layout style and area for programmable application. To adjust different output sinking (driving) currents of the output buffer, different number of fingers of the poly gates in the output NMOS (PMOS) are connected to the ground (VDD). The general layout of the NMOS device in the output cell with the used and unused fingers is shown in FIG. 2(a). The schematic circuit diagram of the layout of FIG. 2(a) is shown in FIG. 2(b), where the used NMOS finger is marked as Mn1 and the unused MOS fingers are lumped as Mn2. To provide a small output current, only a poly gate (used MOS finger) is connected to the pre-buffer circuit to control the NMOS (PMOS) on or off. The other poly gates are connected to VSS (VDD) to keep them off in the layout of FIG. 2(a). Such layout structure has been widely used in IC products, especially in the digital IC's.
Due to the asymmetrical connection on the poly-gate fingers of the output NMOS in the layout, the ESD turn-on phenomenon among the fingers becomes quite different even if the layout is still symmetrical. When such an I/O cell with a small output current driving ability is stressed by ESD, the used NMOS Mn1 is often turned on first due to the transient coupled voltage on its gate. As seen in FIG. 2(b), the ESD voltage applied to the pad is coupled to the gate of Mn1 and Mn2 by the parasitic drain-to-gate overlapped capacitance (see the dashed line as shown in FIG. 2(b)). The coupled gate voltage is kept at the gate of Mn1 by the pre-buffer circuit, but the coupled voltage at the gate of Mn2 is conducted to VSS. Therefore, the Mn2 (with larger device dimension which is designed to protect Mn1) still remains off but the Mn1 (with a smaller device dimension) is turned on to bypass the ESD current from the pad to VSS. This generally causes a very low ESD level for the output buffer, even the output buffer has a large device dimension in total (Mn1+Mn2).
The human body model (HBM) ESD level of an I/O cell library with different driving current specification but the same layout area and layout style is shown in TABLE 2.
TABLE 2HBM2 mA4 mA8 mA12 mA24 mAESD StressBufferBufferBufferBufferBufferVDD (−)1.5 KV  2 KV2.5 KV>2.5 KV>2.5 KVND ModeVSS (+)1.0 KV1.5 KV2.0 KV>2.5 KV>2.5 KVPS Mode
The test data for two worst cases of ESD-testing pin combinations under the PS-mode ESD test and ND-mode ESD test are listed in Table 2 for the I/O cells with different output current specifications. According to the data of Table 2, it is concluded that when the output cell has a higher output current driving ability, the ESD level is also higher. However, the I/O cell with an output current of 2 mA only has an ESD level of 1 kV, even if the total (Mn1+Mn2) device dimension in every cell is the same. To verify the location of ESD damage on the I/O cell with a smaller output current, the ESD-stressed IC was de-layered to find the failure location.
The failure locations were found to locate at the Mn1 device of the I/O cell. However, the Mn2 in the same I/O cell was not damaged by the ESD stress. The detailed analysis on this failure issue is described in the paper by H. -H. Chang, M. -D. Ker and J. -C. Wu, “Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology,” Solid-State Electronics, vol. 43, pp. 375-393, February 1999. This creates a challenge to provide one set of I/O cells with better ESD level. Typically, the HBM ESD level of every I/O cell should be greater than 2 kV under any ESD-testing pin combination.
To improve ESD level of the I/O cells with different output current driving abilities, the descriptions of the gate-coupled technologies had been reported in publications by, e.g., C. Duvvury and R. N. Rountree, “Output buffer with improved ESD protection,” U.S. Pat. No. 4,855,620 (August, 1989); C.-D. Lien, “Electrostatic discharge protection circuit,” U.S. Pat. No. 5,086,365 (February, 1992) M.-D. Ker, C.-Y Wu, T. Cheng, C.-N. Wu, and T.-L. Yu, “Capacitor-couple ESD protection circuit for submicron CMOS IC,” U.S. Pat. No. 5,631,793 (May, 1997); and H.-H. Chang, M.-D. Ker, K. T. Lee, and W.-H. Huang, “Output ESD protection using dynamic-floating-gate arrangement,” U.S. Pat. No. 6,034,552 (March, 2000).
One of such gate-coupled designs is shown in FIG. 3 (U.S. Pat. No. 5,631,793), where the unused Mn2 (Mp2) in the I/O cell with small output current driving ability is connected to VSS (VDD) through the additional resistor Rw2 (Rw1). An additional capacitor Cn (Cp) is added and connected from the pad to the gate of Mn2 (Mp2) to generate the coupling effect. When a positive (negative) ESD voltage in the PS-mode (ND-mode) ESD test condition is applied to the pad, the overstress voltage is coupled to the gate of Mn2 (Mp2) through the added capacitor Cn (Cp). The coupled voltage at the gate of Mn2 (Mp2) is kept longer in time by the resistor Rw2 (Rw1), therefore the unused Mn2 (Mp2) with larger device dimension in the cell layout can be triggered on to discharge the ESD current. So, the gate-coupled technique is used to turn on the Mn2 and Mp2 to discharge ESD current before the Mn1 (Mp1) is damaged by ESD. Because the Mn2 and Mp2 often have much larger device dimensions (channel width of several hundreds of micron), they can sustain a higher ESD stress. The more detailed description on the gate-coupled design is provided in the paper by M.-D. Ker, C.-E. Wu, and H.-H. Chang, “Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC,” IEEE Trans. on VLSI Systems, vol. 4, no.3, pp. 307-321, September, 1996.
Another gate-coupled design to enhance the turn-on of Mn2 and Mp2 is shown in FIG. 4 (U.S. Pat. No. 5,086,365). In FIG. 4, the gate of Mn2 (Mp2) is connected to VSS (VDD) through the Mdn1 (Mdp1) device, which works as a resistor to sustain the coupled voltage in the gate of Mn2 (Mp2). Therefore, the Mn2 (Mp2) can be turned on faster than the Mn1 (Mp1). The ESD current is mainly discharged through the unused Mn2 (Mp2) with large device dimension in the I/O cells.
A more complex design, called as the dynamic-floating-gate technique, was also disclosed to improve ESD level of the I/O cells, which is shown in FIG. 5 (U.S. Pat. No. 6,034,552). In this design, a RC circuit is used to delay the turn-on of the Mdn1 (Mdp1), therefore the ESD-transient voltage can be coupled and held at the gate of Mn2 (Mp2) within a much longer time period. So, the Mn2 (Mp2) can be more effectively turned on to discharge the ESD current from the pad to VSS (VDD). The more detailed principle for this design is disclosed in the paper by H.-H. Chang, M.-D. Ker and J.-C. Wu, “Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology,” Solid-State Electronics, vol. 43, pp.375-393, February. 1999.
The manufacturing process solutions had been also invented for improving the ESD level of such I/O cells. To enhance the turn-on of Mn2, the process method with the additional ESD implantation is also provided to reduce the junction breakdown voltage of the Mn2 device, such as those disclosed in publications by, e.g., C.-C. Hsue and J. Ko, “Method for ESD protection improvement,” U.S. Pat. No. 5,374,565, December 1994; T. A. Lowrey and R. W Chance, “Static discharge circuit having low breakdown voltage bipolar clamp,” U.S. Pat. No. 5,581,104, December 1996; and K.-Z. Chang and C.-Y Lin, “Method of making ESD protection device structure for low supply voltage applications,” U.S. Pat. No. 5,674,761, October 1997.
The NMOS device structure, equivalent circuit, and layout with the additional ESD-implantation method for I/O cells are shown in FIGS. 6(a)-(c), respectively. In FIG. 6(c), the ESD-implantation with a P+ doping concentration is implanted under the drain region of the Mn2 device, but the Mn1 is not implanted. The Mn2 drain to P-well junction with the additional P+ ESD implantation has a lower breakdown voltage. Therefore, the Mn2 can be broken down to discharge ESD current before the Mn1. The ESD current discharging path is shown by the dashed line in FIG. 6(a). To realize this purpose, an additional mask layer is used in the process, and the layout has to be drawn with this ESD-implantation layer. In the layout of FIG. 6(b), the ESD-implantation regions are added at the drain regions of Mn2 fingers, but not on the Mn1 finger. Additional process steps and mask have to be added into the process flow to realize such a design.
When the CMOS technology scaled down to sub-half-micron, the voltage level of VDD in the chip is also reduced to a lower voltage level. Because the I/O signals come from external circuits of chips in a system may have different voltage levels, the high-voltage-tolerant I/O circuits are designed and used in such an interface condition. A typical 3V/5V-tolerant I/O circuit was described in M. Pelgrom and E. Dijkmans, “A 3/5V compatible I/O buffer,” in IEEE Journal of Solid-State Circuits, vol. 30, no.7, pp. 823-825, July 1995; and W. Anderson and D. Krakaauer, “ESD protection for mixed-voltage I/O using NMOS transistors staked in a cascade configuration,” in Proc. Of EOS/ESD Symp., 1998, pp. 54-62.
The design methodology as taught from the above-discussed prior art is focused exclusively on the unused Mn2 in the I/O cell. Although such design methodology can improve the ESD level of the I/O library, it is costly and requires additional elements to realize the gate-coupled circuit or modifications to lower the junction breakdown voltage.